EPIC Architecture and Multimedia
Instruction Sets for
Cryptographic Applications

This PhD thesis (in french) can be download either in PDF (2.3 MB) or in Postscript (9.7 MB).

This thesis is at the intersection of three different domains:

the EPIC processor architecture, and more precisely the IPF processor family from HP and Intel,
the multimedia instruction sets, and especially IPF's and PowerPC G4's (Altivec),
cryptographic algorithms, namely IDEA and RC6.

The main achievements of the thesis are:

study and comparison of multimedia instruction sets, and, especially IPF's and PowerPC G4's ones (Altivec);
study, implementation, and simulation of the cryptographic algorithms IDEA and RC6 on Itanium and PowerPC G4, and a comparison of the experimentally-meseared performance with current implementations;
development of the noptimization and its implementation in SGI's compiler Pro64;
theoretical study and simulation, using an ad hoc tool developped during this thesis, of the cryptographic algorithms IDEA and RC6 on McKinley;
study of McKinley bottlenecks limiting the performance of these algorithms;
study of the problem which now cause the compiler to be unable to exploit the multimedia instructions and proposition of some solution to these problems.

This work is supported by Hewlett-Packard.

This thesis is part of EPFL research project number 1996.2.

¹ IPF (Itanium Processor Family) is the current name of the formely-named IA-64 processor architecture.

Last update: April 19^th, 2002
Jacques-Olivier Haenni
E-mail: haenni@mail.com